1. Technical Field
This disclosure relates to a Single Signal-to-Differential Signal (SS-DS) converter, and more particularly, to a SS-DS converter and a SS-DS converting method which uses a phase interpolation method.
2. Description of the Related Art
A SS-DS converter is a device which receives a single signal as an input signal and outputs two differential signals which have opposite phases to each other, and it is represented by a phase splitter or a phase divider.
Many signals are used in a semiconductor device, and these signals are used as a single signal or a differential signal according to a need. When the single signal is used, there are advantages in that a circuit configuration is simplified and power consumption is low, and so most of the semiconductor devices use the single signal as a basic signal. However, the single signal changes an amount of electrical current consumption according to a signal level and causes induced electromotive force by the parasitic inductance in a power line through which electrical power is supplied. The induced electromotive force is a sort of a noise, and it reduces a voltage margin and a time margin of a signal to restrict an operating speed of a semiconductor device.
On the other hand, the differential signal has constant power consumption, and so using the differential signal can reduce a noise much more than using the single signal. Using the differential signal, it is easy to remove a noise from a signal by using a circuit such as a differential amplifier which amplifies the difference between two signals. The differential signal is used to control a switch of a pipeline, to control a double data rate signaling, or to control a transmission gate of a circuit. When serial data are transferred to an output terminal by sampling parallel data in a SDRAM by using a rising edge and a falling edge of the same output clock like a double data rate SDRAM, only the differential signal can be used as the output clock. However, since in case of the differential signal, two differential signals of the same function should be used, and power consumption is high. Therefore, since power consumption is too high if the differential signal is used to represent all signals of the semiconductor device, the typical semiconductor device uses the single signal as a basic signal and generates and uses the differential signal according to a need. Therefore, many semiconductor devices require a SS-DS converter which converts the single signal to the differential signal when the differential signal is required. Here, the single signal and the differential signal can represent all digital signals such as a clock signal and a data signal.
The performance of the SS-DS converter is relative to the performance of a device in which the SS-DS converter is used and is determined by whether to perform a high speed operation, a skew, a slope of a signal, a duty rate, low power consumption, and the layout area size. The skew denotes a delay time difference that the single signal is applied and the differential signal is outputted. The SS-DS converter receives the single signal and outputs two output signals whose phases are opposite and delay times are same as the differential signals. If a skew which is a delay time difference occurs between the two output signals, an operating time difference occurs in circuits which respectively receive the outputs to operate, and thus it is difficult to perform a normal operation. The slope of the signal relates a time of a rising/falling transition of the differential signal, and if the slope of the signal is small, a timing margin that the circuits which use the differential signal can detect the signal is reduced, whereby a stable operation can not be secured, and power consumption is increased in a CMOS circuit configuration. The duty rate represents a time rate occupied by a certain level during one cycle of a signal of a pulse form. When the signal used for a circuit synchronization such as a clock signal, it is preferable that the duty rate of the signal is set to 50% so that a time of a high level state and a time of a low level state are equal. However, since a PMOS transistor and an NMOS transistor which are usually used in the semiconductor device have a difference in operating characteristics, the duty rate of the signal may often be distorted. A circuit which has received the distorted signal can normally operate only when it operates according to a level having a shorter time among signal levels.
FIG. 1 is a circuit diagram illustrating a SS-DS converter according to a conventional art. The SS-DS converter of FIG. 1 comprises a plurality of inverters Inv1 to Inv5. The two inverters Inv1 and Inv4 constitute a first path through which an input signal sig_in is received and delayed during a predetermined time period, and then a first output signal sig_out is outputted. The three inverters Inv2, Inv3 and Inv5 constitute a second path through which the input signal sig_in is received, delayed during a predetermined period and inverted, and then a second output signal sig_outB having the opposite phase to the input signal sig_in. The first output signal sig_out and the second output signal sig_outB are differential signals which have the opposite phase to each other.
In FIG. 1, since the first path comprises the two inverters Inv1 and Inv4 and the second path comprises the three inverters Inv2, Inv3 and Inv5, and thus the delay times of the first and second paths differ from each other. Since the delay times of the first and second paths differ from each other, the skew occurs between the first output signal sig_out and the second output signal sig_outB, so that a circuit which receives the differential signals sig_out and sig_outB outputted from the SS-DS converter may not operate normally. Therefore, there is a need for removing the skew between the first output signal sig_out and the second output signal sig_outB.
In FIG. 1, in order to remove the skew between the first and second output signals sig_out and sig_outB, the first inverter Inv1 has a different configuration from the other inverters Inv2 to Inv5. That is, used is a delay matching method in which a delay time difference between the first and second output signals sig_out and sig_outB is reduced by adjusting the sizes of the physical inverters between the first and second paths. The delay matching method is a technique in which in the process for adjusting the delay time of the first path to be equal to the delay time of the second path, the PMOS transistor and the NMOS transistor are designed so that delay elements can be matched, so that stable characteristics for a variation on a process, a voltage and a temperature (hereinafter, PVT) is obtained.
In FIG. 1, the third converter Inv3 representatively shows a configuration of the inverters Inv2 to Inv5 except the first inverter Inv1. Each of the inverters Inv2 to Inv5 comprises a PMOS transistor P3 and an NMOS transistor N3 which are serially connected between a power voltage VDD and a ground voltage VSS and receives a signal through a gate terminal. On the other hand, the first inverter Inv1 comprises two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2 which are serially connected between the power voltage VDD and the ground voltage VSS as shown in FIG. 1. The PMOS transistor P1 and the NMOS transistor N1 receive a signal through a gate terminal like the other inverters. However, the PMOS transistor P2 connected to the power voltage VDD receives the ground voltage VSS through a gate terminal, and the NMOS transistor N2 connected to the ground voltage VSS receives the power voltage VDD through a gate terminal. That is, the PMOS transistor P2 and the NMOS transistor N2 are always in an ON state.
The PMOS transistor P2 and the NMOS transistor N2 are provided such that the first inverter Inv1 delays the input signal sig_in by the same time as a time that the second and third inverters Inv2 and Inv3 of the second path delay the input signal sig_in.
In FIG. 1, a skew between the first output signal sig_out and the second output signal sig_outB is reduced such that the first inverter Inv1 is configured differently from the inverters Inv2 to Inv5 and the number and the size of the transistors P1, P2, N1, and N2 which constitute the first inverter Inv1 are adjusted.
The SS-DS converter of FIG. 1 is not suitable for the high speed operation since the slope of the signals from between the first inverter Inv1 and the fourth inverter Inv4 is degraded, and the current lost in the fourth inverter Inv4 which has received the output signal of the first inverter Inv1 which has the low signal slope is large. It handles the PVT variation by using the delay matching method, but since a configuration of the first path and a configuration of the second path are asymmetric, there is a limitation to cope with the PVT variation. The asymmetric structure in the configuration of the first and second paths causes a duty rate distortion of the differential signal.
In FIG. 1, the fourth and fifth inverters Inv4 and Inv5 are output drivers, and the first to third inverters Inv1 to Inv3 are used for a SS-DS converting operation.
FIG. 2 is a circuit diagram illustrating a SS-DS converter according to another conventional art. One of the problems of the SS-DS converter of FIG. 1 is that the first path and the second path are different in the number of the inverters. In order to resolve the problem of the SS-DS converter of FIG. 1, the SS-DS converter of FIG. 2 employs a transmission gate TG1. As shown in FIG. 1, the inverter comprises the MOS gate. Therefore, the transmission gate TG1 which is the MOS gate is added to the first path for delay matching of the first and second paths. Since the transmission gate TG1 is added, a sixth inverter Inv6 which has the same configuration as the inverters Inv2 to Inv5 is used instead of the first inverter Inv1.
The SS-DS converter of FIG. 2 adds the transmission gate TG1 to match the delay times of the first and second paths, but since the output signal of the transmission gate TG1 is different in signal slope from the output signal of the inverter, in order to control this, it is needed to adjust the size of the fourth inverter Inv4. However, adjusting the size of the fourth inverter Inv4 causes an asymmetric structure between the first path and the second path. For these reasons, like the SS-DS converter of FIG. 1, the SS-DS converter of FIG. 2 is not suitable for the high speed operation, and has a limitation to cope with the PVT variation.
FIG. 3 is a circuit diagram illustrating a SS-DS converter which improves upon the SS-DS converter of FIG. 2. As was mentioned above, in the SS-DS converter of FIG. 2, the first path and the second path are asymmetric since the output signal slope of the transmission gate TG1 differs from the output signal slope of the inverter.
In FIG. 3, a buffer Buf1 is added to match the output signal slope of the transmission gate TG1 with the output signal slope of the inverter. The buffer Buf1 comprises an NMOS transistor N4 and a PMOS transistor P4 which are serially connected between the power voltage VDD and the ground voltage VSS. The gate terminals of the NMOS transistor N4 and the PMOS transistor P4 receive an output signal of a sixth inverter Inv6. Since the buffer Buf1 is a delay element which comprises a MOS gate, if the transmission gate TG1 and the buffer Buf1 are independently used, there occurs a delay time difference between the first and second paths due to the delay time of the buffer Buf1. In FIG. 3, in order to prevent the delay time difference caused by the buffer Buf1, the buffer Buf1 is configured such that the gate terminals of the NMOS transistor N4 and the PMOS transistor P4 receive the output signal of the sixth inverter Inv6. Therefore, if the sixth inverter Inv6 inverts and delays the input signal sig_in and outputs the result, the output signal of the sixth inverter Inv6 is simultaneously applied to the transmission gate TG1 and the buffer Buf1, and the output signal of the transmission gate TG1 is added to the output signal of the buffer Buf1, thereby correcting the output signal slope of the transmission gate TG1. Therefore, the signal applied to the fourth inverter Inv4 has a higher slope than the signal applied to the fourth inverter Inv4 of when the transmission gate TG1 is used like FIG. 2. A range for adjusting the size of the fourth inverter Inv4 which is the output driver is significantly reduced compared to the single signal-to-differential signal converter of FIG. 2, and since a signal transitioning time is shorter, power consumption is reduced.
However, as a result of simulating the SS-DS converter of FIG. 3, the waveform of the differential signal is improved compared to the SS-DS converter of FIG. 2, but there is still a need for adjusting the size of the fourth inverter Inv4. Therefore, the first path and the second path are asymmetric in structure, and there is a limitation to cope with the PVT variation, leading to the duty rate distortion.